1. Field of the Invention
This invention relates to an electronic microprocessor system, and in particular to an improved performance memory bus architecture for a microprocessor system.
2. Prior Art
In the field of microprocessors, it is common to have various portions of a microprocessor-based system (such as the microprocessor itself, memory units, and interface circuits for coupling the system to storage units and communications circuits) interconnected by means of one or more communications busses. The prior art teaches various combinations of bus arthitectures, including separate buses for data, address, and control information. However, many microprocessor-based systems use a single integrated bus for data, address, and control information. For example, the Intel Corporation has developed a unified bus architecture known by the trademark "Multibus" for microprocessor system communication.
One problem with such a stardard unified bus architecture is that in certain applications where processing speed is of paramount importance (such as in real-time data processing applications), the unified bus architecture is too slow when fast data transfer between memory and the system microprocessor is desired. The problem arises beceause the unified bus architecture requires a certain protocol for reading and writing data from or to memory, which utilizes an undue amount of time in acknowledging signals from the microprocessor. However, retaining a standard unified bus within the system is advantageous, in that it allows standard circuits and interfaces to be coupled to the microprocessor system.
The present invention is used in conjunction with a standard unified bus, and improves the speed of operation between the system microprocessor and the system memory. This improved performance is achieved by providing a second, separate memory bus apart from the unified system bus but controllably connectable to the unified bus, and by anticipating READ and WRITE commands. A minimum of control signals are required for operation of the secondary memory bus, thus permitting improved processing performance for data transfers between the microprocessor and the system memory.